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Sl.No Project Code DSP Core Projects Action
1 TVMAFE03 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
2 TVREFE19_02 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
3 TVREFE19_05 An Efficient VLSI Architecture For Convolution Based DWT Using MAC View Details
4 TVMAFE07 A 4096-point Radix-4 Memory-based FFT Using DSP Slices View Details
5 TVMAFE19 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
6 TVREFE19_20 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
7 TVMAFE22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
8 TVREFE19_22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
9 TVMAFE23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
10 TVREFE19_23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
11 TVREFE19_27 Digit-serial Versatile Multiplier Based On A Novel Block Recombination Of The Modified Overlap-free Karatsuba Algorithm View Details
12 TVREFE19_38 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
13 TVMAFE38 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
14 TVREFE19_42 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
15 TVREFE19_49 Feed Forward-cut Set-free Pipe Lined Multiply–accumulate Unit For The Machine Learning Accelerator View Details
16 TVREFE19_50 High Performance Multiplier Less Serial Pipelined VLSI Architecture For Real-valued FFT View Details
17 TVREFE19_53 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details
18 TVMAFE45 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details
19 TVMAFE46 A Data-flow Methodology For Accelerating FFT View Details
20 TVMAFE51 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
21 TVMAFE73 Low-complexity Continuous-flow Memory-based FFT Architectures For Real-valued Signals View Details
22 TVMAFE91 A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process View Details
23 TVMAFE92 FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT View Details
24 TVMAFE93 An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation View Details
25 TVMAFE124 An Improved Distributed Multiplier-Less Approach for Radix-2 FFT View Details
26 TVMAFE125 ASIC Implementation of Distributed Arithmetic based FIR Filter using RNS for High Speed DSP systems View Details
27 TVPGFE85 A 4096-point Radix-4 Memory-based FFT Using DSP Slices View Details
28 TVPGFE112 An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation View Details
29 TVPGFE113 An Improved Distributed Multiplier-Less Approach for Radix-2 FFT View Details
30 TVPGFE114 ASIC Implementation of Distributed Arithmetic based FIR Filter using RNS for High Speed DSP systems View Details
31 TVPGFE116 FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT View Details
32 TVMAFE133 FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT View Details
33 TVPGFE117 A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process View Details
34 TVPGFE119 A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT View Details
35 TVMAFE136 A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT View Details
36 TVPGFE145 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC View Details
37 TVMAFE151 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC View Details
38 TVPGFE147 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm View Details
39 TVMAFE155 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm View Details
40 TVPGFE148 Design & Analysis of 16 Bit RISC Processor using Low Power Pipelining View Details
41 TVMAFE157 Design & Analysis of 16 Bit RISC Processor using Low Power Pipelining View Details
42 TVMAFE164 Design Flow for Flip-Flop Grouping in Data-Driven in Clock Gating View Details
43 TVPGFE152 Design of High Performance 64 Bit MAC Unit View Details
44 TVMAFE168 Design of High Performance 64 Bit MAC Unit View Details
45 TVPGFE153 Design of Reversible MAC Unit, Shift and Add Multiplier Using PSDRM Technique View Details
46 TVMAFE170 Design of Reversible MAC Unit, Shift and Add Multiplier Using PSDRM Technique View Details
47 TVPGFE155 FPGA based Partial Reconfigurable FIR Filter Design View Details
48 TVMAFE176 FPGA based Partial Reconfigurable FIR Filter Design View Details
49 TVPGFE156 FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures Using Wallace Tree and Vedic Multipliers View Details
50 TVMAFE177 FPGA Implementation of Scalable Microprogrammed FIR Filter Architectures Using Wallace Tree and Vedic Multipliers View Details
51 TVPGFE160 Low Power Compressor Based MAC Architecture for DSP Applications View Details
52 TVMAFE186 Low Power Compressor Based MAC Architecture for DSP Applications View Details
53 TVPGFE161 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing View Details
54 TVMAFE187 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing View Details

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