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Front End Major Projects
Sl.No Project Code
Arithmetic Core Projects
Action
1 TVMAFE02 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
2 TVMAFE16 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
3 TVMAFE24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
4 TVMAFE28 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
5 TVMAFE65 Factorized Carry Look Ahead Adder View Details
6 TVMAFE86 Design and Analysis of Majority Logic Based Approximate Adders and Multipliers View Details
7 TVMAFE18 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
8 TVMAFE25 Concurrent Error Detectable Carry Select Adder With Easy Testability View Details
9 TVMAFE60 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
10 TVMAFE68 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
11 TVMAFE11 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
12 TVMAFE26 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
13 TVMAFE42 Fast Hub Floating-point Adder For FPGA View Details
14 TVMAFE53 A Design And Implementation Of Montgomery Modular Multiplier View Details
15 TVMAFE63 Design Of Delay Efficient Hybrid Adder For High Speed Applications View Details
16 TVMAFE01 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
17 TVMAFE21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
18 TVMAFE43 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
19 TVMAFE56 A Hardware-efficient Logarithmic Multiplier With Improved Accuracy View Details
20 TVMAFE34 Modified Binary Multiplier Circuit Based On Vedic Mathematics View Details
21 TVMAFE50 16 Bit Power Efficient Carry Select Adder View Details
22 TVMAFE57 A Low Power Binary Square Rooter Using Reversible Logic View Details
23 TVMAFE09 Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers View Details
24 TVMAFE30 Tunable Floating-point Adder View Details
25 TVMAFE35 Rounding Technique Analysis For Power-area & Energy Efficient Approximate Multiplier Design View Details
26 TVMAFE52 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
27 TVMAFE20 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
28 TVMAFE32 Low-power High-accuracy Approximate Multiplier Using Approximate High- Order Compressors View Details
29 TVMAFE71 Implementation Of Addition And Subtraction Operations In Multiple Precision Arithmetic View Details
30 TVMAFE14 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
31 TVMAFE27 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
32 TVMAFE33 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
33 TVMAFE64 Energy Efficient Speed-independent 64-bit Fused Multiply-add Unit* View Details
34 TVMAFE75 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
35 TVMAFE89 Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders View Details
36 TVMAFE107 An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic View Details
37 TVMAFE110 Power Efficient Tiny Yolo CNN using Reduced Hardware Resources based on Booth Multiplier and WALLACE Tree Adders View Details
38 TVMAFE111 High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder View Details
39 TVMAFE112 Design of Approximate Booth Squarer for Error-Tolerant Computing View Details
40 TVMAFE114 Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators View Details
41 TVMAFE115 Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors View Details
42 TVMAFE116 Design of Power Efficient Posit Multiplier View Details
43 TVMAFE118 A Reversible-Logic based Architecture for Artificial Neural Network View Details
44 TVMAFE120 Optimizing FPGA Logic Block Architectures for Arithmetic View Details
45 TVMAFE121 Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology View Details
46 TVMAFE123 Borrow Select Subtractor for Low Power and Area Efficiency View Details
Front End Major Projects
Sl.No Project Code
DSP Core Projects
Action
1 TVMAFE23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
2 TVMAFE46 A Data-flow Methodology For Accelerating FFT View Details
3 TVMAFE13 A High-performance And Energy-efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits View Details
4 TVMAFE37 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
5 TVMAFE19 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
6 TVMAFE38 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
7 TVMAFE03 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
8 TVMAFE22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
9 TVMAFE45 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details
10 TVMAFE07 A 4096-point Radix-4 Memory-based FFT Using DSP Slices View Details
11 TVMAFE51 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
12 TVMAFE73 Low-complexity Continuous-flow Memory-based FFT Architectures For Real-valued Signals View Details
13 TVMAFE91 A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process View Details
14 TVMAFE92 FPGA Implementation for the Multiplexed and Pipelined Building Blocks of Higher Radix-2k FFT View Details
15 TVMAFE93 An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation View Details
16 TVMAFE124 An Improved Distributed Multiplier-Less Approach for Radix-2 FFT View Details
17 TVMAFE125 ASIC Implementation of Distributed Arithmetic based FIR Filter using RNS for High Speed DSP systems View Details
Front End Major Projects
Sl.No Project Code
Communications Projects
Action
1 TVMAFE15 A Probabilistic Parallel Bit-flipping Decoder For Low-density Parity-check Codes View Details
2 TVMAFE17 Error Detection And Correction In SRAM Emulated TCAMs View Details
3 TVMAFE58 Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field View Details
4 TVMAFE82 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
5 TVMAFE05 A Double Error Correction Code For 32-bit Data Words With Efficient Decoding View Details
6 TVMAFE72 Low Power Karnaugh Map Approximate Adder For Error Compensation In Loop Accumulations View Details
7 TVMAFE76 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
8 TVMAFE59 A New Logic For Implementation Of Digital Error Correction Block View Details
Front End Major Projects
Sl.No Project Code
QCA nano Technology Projects
Action
1 TVMAFE39 Design Of An Efficient Multilayer Arithmetic Logic Unit In Quantum-dot Cellular Automata (QCA) View Details
2 TVMAFE44 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
3 TVMAFE87 Design and Analysis of Majority Logic Based Approximate Adders and Multipliers View Details
4 TVMAFE06 Design Of Majority Logic (ML) Based Approximate Full Adders View Details
Front End Major Projects
Sl.No Project Code
Cadence Oriented Projects
Action
1 TVMAFE12 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
2 TVMAFE29 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
3 TVMAFE54 A Design And Implementation Of Montgomery Modular Multiplier View Details
4 TVMAFE62 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
5 TVMAFE10 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
6 TVMAFE47 A Data-flow Methodology For Accelerating FFT View Details
7 TVMAFE49 An Analysis Of DCM-based True Random Number Generator View Details
8 TVMAFE31 Tunable Floating-point Adder View Details
9 TVMAFE96 Codes for Limited Magnitude Error Correction in Multilevel Cell Memories View Details
Front End Major Projects
Sl.No Project Code
Finite State Machines Projects
Action
1 TVMAFE66 FSM Based High Speed VLSI Architecture For DBUTVF Algorithm View Details
Front End Major Projects
Sl.No Project Code
FPGA Applications Projects
Action
1 TVMAFE41 Fast Hub Floating-point Adder For FPGA View Details
2 TVMAFE61 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
3 TVMAFE69 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
4 TVMAFE08 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
5 TVMAFE79 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
6 TVMAFE83 FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator View Details
7 TVMAFE113 Energy-Efficient Low-Latency Signed Multiplier for FPGA-based Hardware Accelerators View Details
8 TVMAFE119 Optimizing FPGA Logic Block Architectures for Arithmetic View Details
Front End Major Projects
Sl.No Project Code
Testing Projects
Action
1 TVMAFE78 A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA View Details
2 TVMAFE40 Chaos-based Bitwise Dynamical Pseudorandom Number Generator On FPGA View Details
3 TVMAFE48 An Analysis Of DCM-based True Random Number Generator View Details
4 TVMAFE77 Study On Early Capture Based VLSI Aging Monitoring Techniques View Details
5 TVMAFE67 On Cyclic Scan Integrity Tests For EDT-based Compression View Details
6 TVMAFE70 Power Estimation Of Embedded SRAMs Using BIST Algorithms View Details
7 TVMAFE88 Reseeding LFSR for Test Pattern Generation View Details
8 TVMAFE55 Design And Implementation Of Low-power High-throughput PRNGs For Security Applications View Details
9 TVMAFE104 Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA View Details
Front End Major Projects
Sl.No Project Code
Matlab Applications Projects
Action
1 TVMAFE81 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
2 TVMAFE85 Image and Video Processing Applications Using Xilinx System Generator View Details
3 TVMAFE80 Design of visible light communication with DCT and M-Ary PAM in Xilinx System Generator View Details
4 TVMAFE84 FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator View Details
5 TVMAFE90 Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing View Details
6 TVMAFE108 Power Efficient Tiny Yolo CNN using Reduced Hardware Resources based on Booth Multiplier and WALLACE Tree Adders View Details
7 TVMAFE117 A Reversible-Logic based Architecture for Artificial Neural Network View Details
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